A semiconductor integrated circuit such as a large-scale integration (LSI) is often designed in order of a logical design being performed and then a physical design being performed, using an electronic design automation (EDA) tool. The physical design includes an arrangement of a logical element and a wiring design. The use of the EDA tool makes it possible to automatically perform a design that satisfies a design rule such as a mask design rule and a timing rule. In recent LSI designing, a conductor called a dummy metal may be inserted between wirings after the arrangement of the logical element and the wiring design in order to improve manufacturing yield for an LSI.
On the other hand, an engineering change order (ECO) is known as a technology that performs a logic change to or a timing modification of a semiconductor integrated circuit. According to the ECO, for example, the addition of or the change in a logical element, or the change in the arrangement of the logical element or the wiring, is performed with respect to data of a designed circuit. Specifically, the ECO after LSI chip manufacturing is called a post-mask ECO. In the post-mask ECO, only a mask of, for example, a portion of wiring layers is updated.
In wiring designing of a semiconductor integrated circuit or a printed-circuit board, a technology is also known that determines a wiring route between two points on the basis of a wiring cost (see, for example, Patent Documents 1 and 2).
Patent Document 1: Japanese Laid-open Patent Publication No. 2000-243838
Patent Document 2: Japanese Laid-open Patent Publication No. 2-133879